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HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
Integrated Device Technology, Inc.
IDT7133SA/LA IDT7143SA/LA
FEATURES:
* High-speed access -- Military: 25/35/45/55/70/90ns (max.) -- Commercial: 20/25/35/45/55/70/90ns (max.) * Low-power operation -- IDT7133/43SA Active: 500 mW (typ.) Standby: 5mW (typ.) -- IDT7133/43LA Active: 500mW (typ.) Standby: 1mW (typ.) * Versatile control for write: separate write control for lower and upper byte of each port * MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 * On-chip port arbitration logic (IDT7133 only) * BUSY output flag on IDT7133; BUSY input on IDT7143 * Fully asynchronous operation from either port * Battery backup operation-2V data retention * TTL-compatible; single 5V (10%) power supply * Available in 68-pin ceramic PGA, 68-pin Flatpack, 68-pin PLCC, and 100-pin TQFP * Military product compliant to MIL-STD-883, Class B * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7143 "SLAVE" Dual-Port in 32-bit-ormore word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200W for a 2V battery. The IDT7133/7143 devices have identical pinouts. Each is packaged in a 68-pin ceramic PGA, a 68-pin flatpack, a 68-pin PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-STD883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
R/WLUB
(2)
CEL
(2)
R/WRUB
(2)
CER
R/WLLB
R/WRLB
(2)
OEL
OER
I/O8L - I/O15L I/O0L - I/O7L
I/O CONTROL
I/O CONTROL
I/O8R - I/O15R I/O0R - I/O7R
BUSYL(1)
A10L A0L ADDRESS DECODER
11
BUSYR(1)
MEMORY ARRAY ADDRESS DECODER
11
A10R A0R
NOTES: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor of 270. IDT7143 (SLAVE): BUSY is input. 2. "LB" designates "Lower Byte" and "UB" designates "Upper Byte" for the R/W signals.
CEL
ARBITRATION LOGIC (IDT7133 ONLY)
CER
2746 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2746/6
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1,2)
I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L VCC R/WLUB R/WLLB
9 8 7 6 5 4 3 2 1
INDEX
68 67 66 65 64 63 62 61 60 59 58 57 56 55
I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R
A10L A9L A8L A7L
54 53 52 51 50 49 48 47 46 45
OEL
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
IDT7133/43 J68-1 & F68-1 PLCC/FLATPACK TOP VIEW(3)
BUSYL
A6L A5L A4L A3L A2L A1L A0L
CEL CER
A0R A1R A2R A3R A4R A5R
BUSYR
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND R/WRUB R/WRLB
A10R A9R A8R A7R A6R
OER
2746 drw 02
I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L
OEL
N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 IDT7133/43 66 10 PN100-1 65 11 12 13 14 15 16 17 18 19
CEL
INDEX
R/WLUB N/C N/C N/C A10L A9L A8L A7L A6L
N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L N/C
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
VCC R/WLLB N/C
100-PIN TQFP TOP VIEW(3)
BUSYL
GND N/C N/C A0R A1R A2R A3R A4R N/C N/C N/C N/C
BUSYR
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R OER R/WRLB GND N/C
R/WRUB N/C N/C N/C A10R A9R A8R A7R A6R A5R
CER
2746 drw 03
NOTES: 1. Both VCC pins must be connected to the supply to ensure reliable operation. 2. Both GND pins must be connected to the supply to ensure reliable operation. 3. This text does not indicate orientation of the actual part-marking.
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)(1,2)
51
50
48
46
44
42
40
38
36
11
53
A6L
52
A5L
49
A3L
47
A1L
45
BUSYL
43
CER
41
A0R
39
A2R
37
A4R
35 34
10
55
A8L
54
A7L
A4L
A2L
A0L
CEL
BUSYR
A1R
A3R
A5R
32
A6R
33
09
A10L
57 56
A9L
A8R
30
A7R
31
08
R/WLLB
59
OEL
58
A10R
28
A9R
29
07
VCC
61
R/WLUB
60
R/WRLB IDT7133/43 GU68-1 PGA TOP VIEW(3)
26
OER
27
06
I/O1L
63
I/O0L
62
GND
24
R/WRUB
25
05
I/O3L
65
I/O2L
64
I/O14R
22
I/O15R
23
04
I/O5L
67
I/O4L
66
I/O12R
20
I/O13R
21
03
I/O7L
68 1
I/O6L
3 5 7 9 11 13 15
I/O10R
18
I/O11R
19
02
I/O8L
2
I/O9L
I/O11L
4 6
I/O13L
8
I/O15L
GND
10
I/O1R
12
I/O3R
14
I/O5R
16
I/O8R
17
I/O9R
01 INDEX A
I/O10L B
I/O12L C
I/O14L D
VCC E
I/O0R F
I/O2R G
I/O4R H
I/O6R J
I/O7R K L
2746 drw 04
NOTES: 1. Both VCC pins must be connected to the supply to ensure reliable operation. 2. Both GND pins must be connected to the supply to ensure reliable operation. 3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port Right Port Names Chip Enable Upper Byte Read/Write Enable Lower Byte Read/Write Enable Output Enable Address Data Input/Output Busy Flag Power Ground
2746 tbl 01
CEL
R/WLUB R/WLLB
CER
R/WRUB R/WRLB
OEL
A0L - A10L I/O0L - I/O15L
OER
A0R - A10R I/O0R - I/O15R
BUSYL
VCC GND
BUSYR
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM
(2)
CAPACITANCE(1)
Unit V
Rating
Commercial
Military -0.5 to +7.0
(TA = +25C, f = 1.0MHZ) TQFP ONLY
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions(2) Max. VIN = 3dV VOUT = 3dV 9 10 Unit pF pF
Terminal Voltage -0.5 to +7.0 with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current 0 to +70 -55 to +125 -55 to +125 2.0 50
TA TBIAS TSTG PT(3) IOUT
-55 to +125 -65 to +135 -65 to +150 2.0 50
C C C W mA
NOTES: 2746 tbl 03 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Commercial Ambient Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2746 tbl 04
NOTES: 2746 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. Unit 5.5 0 6.0 0.8 V V V V
2746 tbl 05
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Either port, VCC = 5.0V 10%)
IDT7133SA IDT7143SA Symbol |ILI| |ILO| VOL VOL VOH Parameter Input Leakage Current
(1)
IDT7133LA IDT7143LA Min. -- -- -- -- 2.4 Max. 5 5 0.4 0.5 -- Unit A A V V V
2746 tbl 06
Test Conditions VCC = 5.5V, VIN = 0V to VCC
Min. -- -- -- -- 2.4
Max. 10 10 0.4 0.5 --
Output Leakage Current Output Low Voltage (I/O0-I/O15) Open Drain Output Low Voltage (BUSY) Output High Voltage
CE = VIH, VOUT = 0V to VCC
IOL = 4mA IOL = 16mA IOH = -4mA
NOTE: 1. At Vcc < 2.0V, input leakages are undefined.
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) (VCC = 5.0V 10%)
IDT7133X20(1) Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports -- TTL Level Inputs) ISB2 Standby Current (One Port -- TTL Level Inputs) ISB3 Full Standby Current (Both Ports -- CMOS Level Inputs) ISB4 Full Standby Current (One Port -- All CMOS Level Inputs) Test Condition Version MIL. S L COM'L. S L MIL. S L IDT7143X20 Max. Typ.(2) - - 250 230 - - 25 25 - - 140 120 - - 1 0.2 - - 140 120 - - 310 280 - - 80 70 - - 200 180 - - 15 5 - - 190 170
(1)
IDT7133X25 IDT7143X25 Typ.(2) Max. 250 230 250 230 25 25 25 25 140 100 140 100 1 0.2 1 0.2 140 120 140 120 330 300 300 270 90 80 80 70 230 190 200 170 30 10 15 4 220 200 190 170
IDT7133X35 IDT7143X35 Typ.(2) Max. 240 220 240 210 25 25 25 25 120 100 120 100 1 0.2 1 0.2 120 100 120 100 325 295 295 250 75 65 70 60 200 180 180 160 30 10 15 4 190 170 170 150 mA mA mA Unit mA
CE = VIL Outputs Open f = fMAX(4) CEL and CER = VIH
f = fMAX(4)
ISB1
mA
COM'L. S L
CE"A" = VIL and CE"B" = VIH(5),
f = fMAX(4), Active Port Outputs Open Both Ports CEL & CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(5)
MIL.
S
L
COM'L. S L MIL. S L
COM'L. S L MIL. S L COM'L. S L
CE"A" < 0.2V and CE"B" > VCC - 0.2V(6)
VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open, f = fMAX(4)
NOTES: 2746 tbl 07 1. Commercial only, 0C to +70C temperature range. 2. VCC = 5V, TA = +25C for Typ., and are not production tested. ICCDC = 180mA (Typ.) 3. "X" in part numbers indicates power rating (SA or LA). 4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) (VCC = 5.0V 10%)
IDT7133X45 Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports -- TTL Level Inputs) ISB2 Standby Current (One Port -- TTL Level Inputs) ISB3 Full Standby Current (Both Ports -- CMOS Level Inputs) ISB4 Full Standby Current (One Port -- All CMOS Level Inputs) Test Condition Version S L COM'L. S L MIL. S L MIL. IDT7143X45 Typ.(2) Max. 230 210 230 210 25 25 25 25 120 100 120 100 1 0.2 1 0.2 120 100 120 100 320 290 290 260 80 70 75 65 210 190 190 170 30 10 15 4 200 180 180 160 IDT7133X55 IDT7143X55 Typ.(2) Max. 230 210 230 210 25 25 25 25 120 100 120 100 1 0.2 1 0.2 120 100 120 100 315 285 285 255 80 70 70 60 210 190 180 160 30 10 15 4 200 180 170 150 IDT7133X70/90 IDT7143X70/90 Typ.(2) Max. 230 210 230 210 25 25 25 25 120 100 120 100 1 0.2 1 0.2 120 100 120 100 310 280 280 250 75 65 70 60 200 180 180 160 30 10 15 4 190 170 170 150 mA mA mA Unit mA
CE = VIL
Outputs Open f = fMAX(4)
ISB1
CEL and CER = VIH
f = fMAX(4)
mA
COM'L. S L
CE"A" = VIL and CE"B" = VIH(5),
f = fMAX(4), Active Port Outputs Open Both Ports CEL & CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(5)
MIL.
S
L
COM'L. S L MIL. S L
COM'L. S L MIL. S L COM'L. S L
CE"A" < 0.2V and CE"B" > VCC - 0.2V(6)
VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open, f = fMAX(4)
NOTES: 2746 tbl 07 1. Commercial only, 0C to +70C temperature range. 2. VCC = 5V, TA = +25C for Typ., and are not production tested. ICCDC = 180mA (Typ.) 3. "X" in part numbers indicates power rating (SA or LA). 4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using "AC Test Conditions" of input levels of GND to 3V. 5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
IDT7133LA/IDT7143LA Symbol VDR ICCDR tCDR(3) tR
(3)
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Test Condition VCC = 2V
Min. 2.0 -- -- 0 tRC
(2)
Typ. -- 100 100 -- --
Max. -- 4000 1500 -- --
Unit V A ns ns
2746 tbl 08
CE VHC
VIN VHC or VLC
MIL. COM'L.
NOTES:
1. Vcc = 2V, TA = +25C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed but is not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE VCC tCDR 4.5V VDR 2V VDR VIH VIH
2746 drw 05
4.5V tR
CE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1, 2, and 3
2746 tbl 09
5V 1250 DATAOUT 775 30pF DATAOUT 775
5V 1250
5V 270
BUSY
5pF* 30pF
2746 drw 06
Figure 1. AC Output Load
Figure 2. Output Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig
Figure 3.
BUSY AC Output Load (IDT7133 only)
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
IDT7133X20(2) IDT7143X20(2) Min. Max. 20 -- -- -- 3 3 --
(3) (3)
Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1, 3)
IDT7133X25 IDT7143X25 Min. Max. 25 -- -- -- 0 0 -- 0 -- -- 25 25 15 -- -- 15 -- 50
IDT7133X35 IDT7143X35 Min. Max. 35 -- -- -- 0 0 -- 0 -- -- 35 35 20 -- -- 20 -- 50
Unit ns ns ns ns ns ns ns ns ns
-- 20 20 12 -- -- 12 -- 20
Output High-Z Time(1, 3) Chip Enable to Power Up Time Chip Disable to Power Down Time
0 --
Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1, 3)
IDT7133X45 IDT7143X45 Min. Max. 45 -- -- -- 0 0 -- 0 -- -- 45 45 25 -- -- 20 -- 50
IDT7133X55 IDT7143X55 Min. Max. 55 -- -- -- 0 5 -- 0 -- -- 55 55 30 -- -- 20 -- 50
IDT7133X70/90 IDT7143X70/90 Min. Max. 70/90 -- -- -- 0/0 5/5 -- 0/0 -- -- 70/90 70/90 40/40 -- -- 25/25 -- 50/50
Unit ns ns ns ns ns ns ns ns ns
2746 tbl 10
Output High-Z Time(1, 3) Chip Enable to Power Up Time(3) Chip Disable to Power Down Time(3)
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. 0C to +70C temperature range only. 3. This parameter is guaranteed by device characterization, but is not production tested. 4. "X" in part number indicates power rating (SA or LA).
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1, 2, 4, 5)
tRC ADDRESS tAA
tOH DATAOUT PREVIOUS DATA VALID
tOH DATA VALID
BUSYOUT
tBDD
(3,4) 2746 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3, 5)
tACE
CE
tAOE
(4)
tHZ
(2)
OE
tLZ DATAOUT tLZ tPU CURRENT ICC 50% ISB 50%
2746 drw 08 (1) (1)
tHZ VALID DATA tPD
(4)
(2)
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deasserted last, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/W = VIH and the address is valid prior to or coincident with CE transition Low.
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time(4) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width(6) Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1,3) Data Hold Time(5) Write Enable to Output in High-Z(1,3) Output Active from End-of-Write(1,3,5) 20 15 15 0 15 0 15 -- 0 -- 0 -- -- -- -- -- -- -- 12 -- 12 -- 25 20 20 0 20 0 15 -- 0 -- 0 -- -- -- -- -- -- -- 15 -- 15 -- 35 25 25 0 25 0 20 -- 0 -- 0 -- -- -- -- -- -- -- 20 -- 20 -- ns ns ns ns ns ns ns ns ns ns ns Parameter IDT7133X20(2) IDT7143X20(2) Min. Max. IDT7133X25 IDT7143X25 Min. Max. IDT7133X35 IDT7143X35 Min. Max. Unit
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time(4) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width
(6)
Parameter
IDT7133X45 IDT7143X45 Min. Max. 45 30 30 0 30 0 20 -- 5 -- 5
(1,3,5)
IDT7133X55 IDT7143X55 Min. Max. 55 40 40 0 40 0 25 -- 5 -- 5 -- -- -- -- -- -- -- 20 -- 20 --
IDT7133X70/90 IDT7143X70/90 Min. Max. 70/90 50/50 50/50 0/0 50/50 0/0 30/30 -- 5/5 -- 5/5 -- -- -- -- -- -- -- 25/25 -- 25/25 --
Unit ns ns ns ns ns ns ns ns ns ns ns
-- -- -- -- -- -- -- 20 -- 20 --
Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time(5) Write Enable to Output in High-Z(1,3) Output Active from End-of-Write
(1,3)
NOTES: 2746 tbl 11 1. Transition is measured 500mV from Low or High-impedance voltage from the Output Test Load (Figure 2).. 2. 0 C to +70C temperature range only. 3. This parameter is guaranteed by device characterization but is not production tested. 4. For MASTER/SLAVE combination, tWC = tBAA + tWR + tWP, since RW = VIL must occur after tBAA. 5. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will very over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 6. This parameter is determined by device characterization, but is not production tested. Transition is measured 200mV from steady state with the Output Test Load (Figure 2). 7. "X" in part number indicates power rating (SA or LA).
6.14
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
IDT7133X20(1) IDT7143X20(1) Min. Max. -- -- -- -- --
(2)
Symbol tBAA tBDA tBAC tBDC tWDD tDDD tBDD tAPS tWH
Parameter Access Time from Address Disable Time from Address Access Time from Chip Enable Disable Time from Chip Enable
IDT7133X25 IDT7143X25 Min. Max. -- -- -- -- -- -- -- 5 20 20 20 20 20 50 35 30 -- --
IDT7133X35 IDT7143X35 Min. Max. -- -- -- -- -- -- -- 5 25 30 30 25 25 60 45 35 -- --
Unit ns ns ns ns ns ns ns ns ns
BUSY TIMING (For MASTER IDT7133)
BUSY BUSY BUSY BUSY
20 20 20 17 40 30 25 -- --
Write Pulse to Data Delay(2) Write Data Valid to Read Data Delay
BUSY
-- -- 5 20
Disable to Valid Data(3)
(4) (6)
Arbitration Priority Set Up Time Write Hold After BUSY Input to Write(5)
(6) (2)
BUSY INPUT TIMING (For SLAVE IDT7143) tWB tWH tWDD tDDD
BUSY
0 20 -- --
-- -- 40 30
0 20 -- --
-- -- 50 35
0 25 -- --
-- -- 60 45
ns ns ns ns
2746 tbl 12
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay(2)
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
Symbol tBAA tBDA tBAC tBDC tWDD tDDD tBDD tAPS tWH Parameter Access Time from Address Disable Time from Address Access Time from Chip Enable Disable Time from Chip Enable
(2)
IDT7133X45 IDT7143X45 Min. Max. -- -- -- -- -- -- --
(4)
IDT7133X55 IDT7143X55 Min. Max. -- -- -- -- -- -- -- 5 30 40 40 35 30 80 55 40 -- --
IDT7133X70/90 IDT7143X70/90 Min. Max. -- -- -- -- -- -- -- 5/5 30/30 45/45 45/45 35/35 30/30 90/90 70/70 40/40 -- --
Unit ns ns ns ns ns ns ns ns ns
BUSY TIMING (For MASTER IDT7133)
BUSY BUSY BUSY BUSY
40 40 30 25 80 55 40 -- --
Write Pulse to Data Delay
Write Data Valid to Read Data Delay(2)
BUSY
Disable to Valid Data
(3)
Arbitration Priority Set Up Time Write Hold After BUSY(6)
5 30
BUSY INPUT TIMING (For SLAVE IDT7143) tWB tWH tWDD tDDD
BUSY
Input to Write(5)
(6)
0 30 -- --
-- -- 80 55
0 30 -- --
-- -- 80 55
0/0 30/30 -- --
-- -- 90/90 70/70
ns ns ns ns
2746 tbl 12
Write Hold After BUSY Write Pulse to Data Delay(2) Write Data Valid to Read Data Delay(2)
NOTES: 1. 0C to +70C temperature range only. 2. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and Busy". 3. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual). 4 To ensure that the earlier of the two ports wins. 5. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 6. To ensure that a write cycle is completed on port "B" after contention on port "A". 7. "X" in part number indicates power rating (SA or LA).
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)(1, 5, 8)
tWC ADDRESS tAS
(6)
W
OE
tAW
tWR
(3)
CE
tWP R/W
(9) (2)
tHZ
(7)
tLZ DATAOUT
(4)
tWZ (7) tOW
(4)
tHZ
(7)
tDW DATAIN
tDH
2746 drw 09
WRITE CYCLE NO. 2 (CE CONTROLLED TIMING)(1, 5) CE
tWC ADDRESS tAW
CE
R/W
(9)
tAS
(6)
tEW
(2)
tWR
tDW DATAIN
tDH
2746 drw 10
NOTES: 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output Test Load (Figure 2). 8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. R/W for either upper or lower byte.
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (1, 2, 3)
tWC ADDR "A" MATCH tWP R/W "A" tDW DATAIN "A" tAPS ADDR "B"
(1)
tDH VALID
MATCH tBDA tBDD
BUSY "B"
tWDD DATAOUT "B" tDDD
(4)
2746 drw 11
VALID
NOTES: 1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY (M/S = VIL) S
tWP R/W "A" tWB
BUSY
"B"
tWH
(1)
R/W "B"
(2)
2746 drw 12
NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W "B", until BUSY "B" goes High. 3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING
ADDR "A" AND "B" ADDRESSES MATCH
(1)
CE
"A"
tAPS
CE "B"
tBAC
BUSY
tBDC
2746 drw 13
"B"
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESSES
tRC OR ADDR "A" tWC ADDRESSES DO NOT MATCH
(1)
ADDRESSES MATCH tAPS
ADDR "B" tBAA tBDA
2746 drw 14
BUSY "B"
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT7133 only).
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IDT7133/43 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7133/43 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE High). When a port is enabled, access to the entire memory array is permitted. Non-contention READ/WRITE conditions are illustrated in Truth Table I.
LEFT RIGHT
R/W
R/WL
IDT7133 MASTER
R/WR
R/W
BUSY
270
BUSYL
+5V
BUSYR
270
BUSY
+5V
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by using the IDT7143 (SLAVE). In the IDT7143, the busy pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 7133 RAM are open drain and require pull-up resistors.
R/WL
IDT7142 IDT7143 (1) SLAVE
R/WR
BUSYL
BUSYR
2746 drw 15
Figure 4. Busy and chip enable routing for both width and depth expansion with the IDT7133 (MASTER) and the IDT7143 (SLAVE).
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding an IDT7133/43 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7133 RAM the busy pin is an output and on the IDT7143 RAM, the busy pin is an input (see Figure 4).
Expanding the data bus width to 32 bits or more in a DualPort RAM system implies that several chips will be active at the same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its BUSYL while another activates its BUSYR signal. Both sides are now busy and the CPUs will await indefinitely for their port to become free. To avoid the "Busy Lock-Out" problem, IDT has developed a MASTER/SLAVE approach where only one hardware arbitrator, in the MASTER, is used. The SLAVE has BUSY inputs which allow an interface to the MASTER with no external components and with a speed advantage over other systems. When expanding Dual-Port RAMs in width, the writing of the SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a contention situation. Conversely, the write pulse must extend a hold time past BUSY to ensure that a write cycle takes place after the contention is resolved. This timing is inherent in all Dual-Port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to BUSY from the MASTER.
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I -- NON-CONTENTION READ/WRITE CONTROL(4)
LEFT OR RIGHT PORT(1) R/WLB W X X L L H L H H H R/WUB W X X L H L H L H H
CE OE
I/O0-7 Z Z DATAIN DATAIN DATAOUT DATAIN Z Z
I/O8-15 Z Z DATAIN DATAOUT DATAIN Z DATAIN Z
Function Port Disabled and in Power Down Mode, ISB2, ISB4
CER
H H L L L L L L L
X X X L L H H L H
= CEL = VIH, Power Down Mode, ISB1 or ISB3
Data on Lower Byte and Upper Byte Written into Memory(2) Data on Lower Byte Written into Memory(2), Data in Memory Output on Upper Byte(3) Data in Memory Output on Lower Byte(3), Data on Upper Byte Written into Memory(2) Data on Lower Byte Written into Memory(2) Data on Upper Byte Written into Memory(2) Data in Memory Output on Lower Byte and Upper Byte High Impedance Outputs
2746 tbl 13
DATAOUT DATAOUT
NOTES: 1. A0L - A10L A0R - A10R. 2. If BUSY = VIL, data is not written. 3. If BUSY = VIL, data may not be valid, see tWDD and tDDD timing. 4. "H" = VIH, "L" = VIL, "X" = Don't Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte.
TRUTH TABLE II -- ADDRESS BUSY ARBITRATION
Inputs
CEL CE CER CE
Outputs
BUSYL BUSY
A0L-A10L A0R-A10R
NO MATCH MATCH MATCH MATCH
(1)
BUSYR BUSY
(1)
Function Normal Normal Normal Write Inhibit(3)
X H X L
X X H L
H H H (2)
H H H (2)
NOTES: 2746 tbl 14 1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
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IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B 68-pin PLCC (J68-1) 68-pin PGA (G68-1) 68-pin Flatplack (F68-1) 100-pin TQFP (PN100-1) Commercial Only Speed in nanoseconds
J G F PF 20 25 35 45 55 70 90 LA SA 7133 7143
Low Power Standard Power 32K (2K x 16-Bit) MASTER Dual-Port RAM 32K (2K x 16-Bit) SLAVE Dual-Port RAM
2746 drw 16
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